The SH-4 (SH7750) has been developed as the top-end model in the SuperH RISC engine
family, featuring a 128-bit graphic engine for multimedia applications and 360 MIPS performance.
The SH7750 CPU has a RISC type instruction set, and features upward-compatibility at the object
code level with SH-1, SH-2, SH-3, and SH-3E microcomputers.

In addition to single- and double-precision floating-point operation capability, the on-chip FPU
has a 128-bit graphic engine that enables 32-bit floating-point data to be processed 128 bits at a
time. It also supports 4 4 array operations and inner product operations, enabling a performance
of 1.4 GFLOPS to be achieved.

A superscalar architecture is employed that enables simultaneous execution of two instructions
(including FPU instructions), providing performance of up to twice that of conventional
architectures at the same frequency.

SH7750 on-chip peripheral modules include oscillator circuits, an interrupt controller (INTC),
direct memory access controller (DMAC), timer unit (TMU), real-time clock (RTC), serial
communication interfaces (SCI, SCIF), and a user break controller (UBC), enabling a user system
to be configured with a minimum of components.

An 8-kbyte instruction cache and 16-kbyte data cache are also provided, and the on-chip memory
management unit (MMU) handles translation from the 4-Gbyte virtual address space to the
physical address space. The bus state controller (BSC) supporting external memory access can
handle a 64-bit synchronous DRAM 4-bank system and 64-bit data bus as well as ROM, SRAM,
DRAM, synchronous DRAM, and PCMCIA.

Consult your Hitachi sales representative for information on development environment

SuperH is a trademark of Hitachi, Ltd.

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